The present invention relates generally to signal processing, and more particularly to the use of pulse density modulation circuits to convert digital signals into analog signals.
In electronic circuits, digital signals are commonly converted to analog signals using digital-to-analog converters (DACs). Conventional DACs, sometimes referred to as “static” DACs, receive and process digital input data using discrete hardware components to generate an analog signal that represents the digital input data. The voltage level of the analog signal varies according to the digital input signal. For example, a two-bit static DAC with a voltage range from zero to five volts provides an analog output from zero to five volts in increments based upon the value of an digital input word. As the number of bits in the digital input word increases, the size of the analog increments decreases. One of the problems with static DACs is that the discrete hardware components require a relatively large amount of space and consume a relatively large amount of power, making them unsuitable for applications that require compact, integrated solutions, such as personal communications services (PCS) devices.
One alternative to a static DAC is the “digital-based” DAC. In general, digital-based DACs require relatively less power and space than their static DAC counterparts, making digital based converters particularly well suited for small, integrated applications. Two modulation approaches used in digital-based DACs are pulse width modulation (PWM) and pulse density modulation (PDM).
PWM involves processing an N-bit input value to generate an analog signal with a voltage level that is proportional to the N-bit input value. A typical PWM modulator includes an N-bit counter, an N-bit comparator and a filter. The N-bit input value is applied to one of the comparator inputs. The output of the counter is applied to the other comparator input. The comparator compares the magnitude of the N-bit input value to the magnitude of the counter output to generate a single bit periodic signal.
A characteristic of PWM that presents some practical difficulties is that all of the logic HIGHs and LOWs (“1”s and “0”s) are contiguous within a modulation cycle. This characteristic is represented in the analog output as an AC component, which is often referred to as “ripple,” typically expressed as a percentage of the logic HIGH voltage level. Ideally, the analog output is a constant DC value. However, because of the contiguous nature of the logic HIGHs and LOWs in the analog output, the analog output of a PWM modulator often contains AC ripple. The cutoff frequency of the filter is often lowered to attenuate ripple. However, this requires increasing the time constant of the filter, which can significantly increase the response time of the filter and in some cases cause instability in control loops, making it unsuitable for high speed applications.
In a pulse density modulation (PDM) system, it is the relative density of the pulses that correspond to the amplitude of the analog signal. In a PDM bitstream, a signal “1” corresponds to a pulse, while a signal “0” corresponds to an absence of a pulse. A run of all “1”s would result in a positive amplitude value, while a run of all “0”s would result in a negative amplitude value. Alternatively, a string of alternating “1”s and “0”s would correspond to a zero amplitude value. Thus, the bitstream actually looks like the wave it represents.
A PDM signal needs to be demodulated into an analog signal. Typically, the PDM digital bitstream is passed through an analog low pass filter that averages the signal. The density of pulses is then measured by the average amplitude of those pulses over time. As such, the decoding process only requires a low pass filter. PDM is similar to PWM except that the ripple in the analog output is characteristically lower than in a comparable PWM analog signal.
Although the PDM approach provides improved performance over the PWM approach, it has disadvantages. One of the problems with the conventional PDM circuit is that the conventional PDM output circuit requires a dedicated dead zone circuit to prevent shorts between VCC and GND during output switching. Also, the output has limited resolution due to the use of only two states in the output circuit (VCC and GND). Furthermore, the conventional PDM output switching circuit produces excessive switching noise which lowers the signal-to-noise ratio (SNR), and consumes unnecessary power especially at low output voltage levels due to the frequent switching between VCC and GND.
Therefore, what is desirable in the art of digital-based DAC designs are improved PDM DAC circuit designs that eliminate the need of a dead zone circuit, improved output resolution, SNR, switching noise and power consumption.